The present invention relates to a semiconductor device and more particularly, to a fabrication method for a semiconductor device with an increased channel area and a fabrication method thereof.
In general, for semiconductor devices, as miniaturization has decreased the design rule, the concentration of boron in the channel regions has increased, leading to an increase in the electric field. This is especially true for dynamic random access memory (DRAM) cell and planar type N-channel metal-oxide semiconductor field effect transistors (NMOSFETs). As a result, it is often difficult to obtain an acceptable refresh time.
Due to large scale of integration of semiconductor devices (e.g., DRAMs), feature size tends to decrease while doping concentration tends to increase. This increase causes the electric field of the semiconductor device to increase. The increase in the electric field, however, also increases junction leakage.
Also, since channel lengths and widths are often constrained, channel doping is increasingly applied to meet the required technical features. As a result, mobility of electrons is likely to decrease. This decrease in mobility makes it difficult to obtain the required current flow through channels.
FIG. 1A illustrates a top view of a semiconductor device with a conventional planar NMOSFET. FIG. 1B illustrates a sectional view of the semiconductor device taken from cut plane A-A′ illustrated in FIG. 1A. A shallow trench isolation (STI) process is performed on a region of substrate 11 to form an isolation structure 12 (e.g., field oxide layer). A gate oxide layer 13 is formed on an active region 11A of the substrate 11 defined by the isolation structure 12. Planar type gates PG each including a gate electrode 14 and a gate hard mask 15 stacked over each other in this sequence order are formed on the gate oxide layer 13. Within the active region 11A, N-type source and drain regions S and D are formed on both sides of each of the planar type gates PG.
As illustrated and described above, since the planar type gates PG are formed on the flat surface of the active region 11A of the substrate 11, they are often called NMOSFETs with planar channels. However, due to large scale integration, the planar type transistor structure often has difficulty in obtaining the desired channel length and width. Thus, a short (or narrow) channel effect may not be blocked.
Recess channel array transistors (RCATs) or FinFETs are suggested to overcome the above limitation. Although these suggested transistor structures are capable of increasing the channel area by using three surfaces of the active region, these structures may not be enough to increase the channel area up to a certain level due to the high integration.